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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Advance Information
MCM63P636
64K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM
The MCM63P636 is a 2M-bit synchronous fast static RAM designed to provide burstable, high performance, secondary cache for advanced microprocessors. It is organized as 64K words of 36 bits each. This device integrates input registers, an output register, a 2-bit address counter, and a high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows for precise cycle control with the use of an external clock (K) and external strobe clock (SK). Addresses (SA), data inputs (DQx), and all control signals are clock (K) controlled through positive-edge-triggered noninverting registers. Data strobes STRBA, STRBA, STRBB, and STRBB are strobe clock (SK) controlled through positive-edge-triggered non-inverting registers. Strobe clock, 180 degrees out of phase with clock (K), is only used with the data strobes such that they are centered with data output on read cycles. Burst sequences are initiated with ADS input pin, and subsequent burst addresses are generated internally by MCM63P636. Write cycles are internally self-timed and are initiated with address and control logic by the rising edge of the clock (K) input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. Special logic enables the memory to accept data on the rising edge of clock (K) a cycle after address and control signals. For read cycles, the SRAMs output data is temporarily stored by an edge-triggered output register and then released to the output buffers at the second rising edge of clock (K) for a read latency of three cycles. Data strobes rise and fall with SRAM output to help external devices receiving the data to latch the data. The MCM63P636 operates from a 3.3 V core power supply, a 2.0 V input power supply, and a 2.0 V I/O power supply. These power supplies are designed so that power sequencing is not required. * MCM63P636-250 = 3.9 ns Access/4 ns Cycle (250 MHz) MCM63P636-225 = 4.3 ns Access/4.4 ns Cycle (225 MHz) MCM63P636-200 = 4.9 ns Access/5 ns Cycle (200 MHz) * 3.3 V 200 mV VDD Supply, 2.0 V VDDI and VDDQ Supply * Internally Self-Timed Late Write Cycle * Three-Cycle Single-Read Latency * Strobe Clock Input and Data Strobe Output Pins * On-Chip Output Enable Control * On-Chip Burst Advance Control * Four-Tick Burst * Power-On Reset Pin * Low Power Stop Clock Operation * Boundary Scan (PBGA Only) * JEDEC Standard 153-Pin PBGA and 100-Pin TQFP Packages
ZP PACKAGE PBGA CASE 1107-01
TQ PACKAGE TQFP CASE 983A-01
This document contains information on a new product. Specifications and information herein are subject to change without notice.
3/16/98
(c) Motorola, Inc. 1998 MOTOROLA FAST SRAM
MCM63P636 1
PBGA PIN ASSIGNMENT
1 A VSS VDDQ B DQa C D E F G H J K L M N P R T U DQa SA SE3 NC NU/VDD SA DQb DQb VSS DQb VSS DQb VSS DQb VSS DQb VSS DQb VSS DQb VSS DQb VSS VSS VDDQ VSS NU/VSS W DQa VSS DQa VSS DQa DQa DQa VDD VSS RESET VSS VDDQ DQb DQb SA SE1 SE2 NC SA VDDQ VSS 2 3 4 5 6 7 8 9
ADS VDD VSS K SK VSS VDD VSS
VDDQ VDD
VDD VDDQ VDDI DQb
DQa VDDI VDD VDDQ VDD VSS
VDD VDDQ
DQa STRBA VDD VSS
VDD STRBB DQb VSS VDDQ
VSS VDDQ VSS DQa
VSS NU/VSS VSS NC VSS SA SA SA SA1 SA0 TCK
DQa STRBA VDD VSS VDD
VDD STRBB DQb VSS VDD VSS SA SA SA TRST VDD VDDQ VDDI DQb VDD VDDQ DQb DQb
VSS VDDQ VDD DQa DQa VDDI
VSS VDDQ VDD VSS DQa DQa DQa SA SA SA TMS
VSS VDDQ VSS DQa DQa SA TDI
VSS VDDQ NC DQb
VSS VDDQ
TDO VDDQ
153-BUMP PBGA TOP VIEW
MCM63P636 2
MOTOROLA FAST SRAM
TQFP PIN ASSIGNMENT
SA SA SE1 SE2 NU/V SS NU/V SS VDDI SK SE3 V DD VSS K W VDDI NC ADS RESET NU/V DD SA SA DQa DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa STRBA VDD STRBA VSS DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa DQa 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC SA SA SA SA SA1 SA0 VDDI NC VSS VDD NC VDDI SA SA SA SA SA SA NC
DQb DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS STRBB VDD STRBB DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb DQb
MOTOROLA FAST SRAM
MCM63P636 3
PBGA PIN DESCRIPTIONS
Pin Locations 5D (a) 1B, 2B, 1D, 2D, 3D, 1F, 2F, 1H, 2H, 1K, 2K, 1M, 2M, 1P, 2P, 3P, 1T, 2T (b) 8B, 9B, 7D, 8D, 9D, 8F, 9F, 8H, 9H, 8K, 9K, 8M, 9M, 7P, 8P, 9P, 8T, 9T 5F 6C 3A, 7A, 3B, 7B, 5M, 5N, 4P, 5P, 6P, 4R, 6R, 3T, 4T, 6T 5R, 5T Symbol ADS DQx Type Input I/O Description Synchronous Address Status: Active low, used to initiate read or write state machines latch in external addresses, or deselect chip. Synchronous Data I/O: "x" refers to the word being read or written (I/Os a and b).
K RESET SA SA1, SA0
Input Input Input Input
Clock: This signal registers the address, data in, and all control signals. Asynchronous Power-On Reset: Active low at power up, resets internal state machines. Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. Synchronous Address Inputs: These pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. Synchronous Chip Enable: Active low to enable chip. Synchronous Chip Enable: Active high to enable chip. Synchronous Chip Enable: Active low to enable chip. Data Strobe Clock: 180 degrees out-of-phase with K. Used only with data strobes. Data Strobe: Used in reference to DQa I/Os. Data Strobe: Used in reference to DQa I/Os. Data Strobe: Used in reference to DQb I/Os. Data Strobe: Used in reference to DQb I/Os. Boundary Scan Pin, Test Clock: If boundary scan is not used, TCK must be tied to VDD or VSS. Boundary Scan Pin, Test Data In. Boundary Scan Pin, Test Data Out. Boundary Scan Pin, Test Mode Select. Boundary Scan Pin, Asynchronous Test Reset. If boundary scan is not used, TRST must be tied to VSS. Synchronous Write. Core Power Supply. Input Power Supply. I/O Power Supply. Ground.
4A 5A 4B 5G 3K 3H 7K 7H 5U 3U 7U 4U 6U 5C 4D, 6D, 3E, 7E, 4F, 6F, 3G, 7G, 4H, 6H, 4K, 6K, 3L, 7L, 4M, 6M, 3N, 7N 3F, 7F, 3M, 7M 2A, 8A, 2C, 8C, 2E, 8E, 2G, 8G, 2J, 8J, 2L, 8L, 2N, 8N, 2R, 8R, 2U, 8U 1A, 9A, 1C, 3C, 7C, 9C, 1E, 4E, 5E, 6E, 9E, 1G, 4G, 6G, 9G, 5H, 1J, 3J, 4J, 6J, 7J, 9J, 1L, 4L, 5L, 6L, 9L, 1N, 4N, 6N, 9N, 1R, 3R, 7R, 9R, 1U, 9U 6A, 5B, 5K, 7T 6B 4C, 5J
SE1 SE2 SE3 SK STRBA STRBA STRBB STRBB TCK TDI TDO TMS TRST W VDD VDDI VDDQ VSS
Input Input Input Input Output Output Output Output Input Input Output Input Input Input Supply Supply Supply Supply
NC NU/VDD NU/VSS
-- -- --
No Connection: There is no connection to the chip. Not Usable: There is an internal connection to the chip. This pin may be left unconnected or tied to VDD. Not Usable: There is an internal connection to the chip. This pin may be left unconnected or tied to VSS.
MCM63P636 4
MOTOROLA FAST SRAM
TQFP PIN DESCRIPTIONS
Pin Locations 85 (a) 1, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23, 24, 25, 28, 29, 30 (b) 51, 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73, 74, 75, 78, 79, 80 89 84 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 81, 82, 99, 100 36, 37 Symbol ADS DQx Type Input I/O Description Synchronous Address Status: Active low, used to initiate read or write state machines latch in external addresses, or deselect chip. Synchronous Data I/O: "x" refers to the word being read or written (I/Os a and b).
K RESET SA SA1, SA0
Input Input Input Input
Clock: This signal registers the address, data in, and all control signals. Asynchronous Power-On Reset: Active low at power up, resets internal state machines. Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. Synchronous Address Inputs: These pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. Synchronous Chip Enable: Active low to enable chip. Synchronous Chip Enable: Active high to enable chip. Synchronous Chip Enable: Active low to enable chip. Data Strobe Clock: 180 degrees out-of-phase with K. Used only with data strobes. Data Strobe: Used in reference to DQa I/Os. Data Strobe: Used in reference to DQa I/Os. Data Strobe: Used in reference to DQb I/Os. Data Strobe: Used in reference to DQb I/Os. Synchronous Write. Core Power Supply. Input Power Supply. I/O Power Supply. Ground. No Connection: There is no connection to the chip. Not Usable: There is an internal connection to the chip. This pin may be left unconnected or tied to VDD. Not Usable: There is an internal connection to the chip. This pin may be left unconnected or tied to VSS.
98 97 92 93 16 14 64 66 88 15, 41, 65, 91 38, 43, 87, 94 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 31, 39, 42, 50, 86 83 95, 96
SE1 SE2 SE3 SK STRBA STRBA STRBB STRBB W VDD VDDI VDDQ VSS NC NU/VDD NU/VSS
Input Input Input Input Output Output Output Output Input Supply Supply Supply Supply -- -- --
MOTOROLA FAST SRAM
MCM63P636 5
TRUTH TABLE (See Notes 1 and 2)
K L-H L-H L-H L-H L-H E False True True X X ADS 0 0 0 1 1 W X 0 1 0 1 Next Cycle (n) Deselect Load Address, Begin Write Load Address, Begin Read Continue Write Continue Read Mask Write Input Command Code D BW BR CW CR MW DQ (n + 1) High-Z Data In -- Data In -- High-Z DQ (n+2) -- -- Data Out -- Data Out --
NOTES: 1. X = don't care, 1 = logic high, 0 = logic low. 2. E = true if SE1 and SE3 = 0, and SE2 = 1.
BURST ADDRESS TABLE
1st Address (External) X . . . X00 X . . . X01 X . . . X10 X . . . X11 2nd Address (Internal) X . . . X01 X . . . X00 X . . . X11 X . . . X10 3rd Address (Internal) X . . . X10 X . . . X11 X . . . X00 X . . . X01 4th Address (Internal) X . . . X11 X . . . X10 X . . . X01 X . . . X00
D, CW, CR - MW
BR DESELECT BW
NEW READ* CR
NEW WRITE* CW MW
BURST READ 1* CR
BURST WRITE 1* MW CW
MASKED WRITE 1* MW
BURST READ 2* CR BR BURST READ 3* BW D, CW, MW
BURST WRITE 2* MW CW
MASKED WRITE 2* MW
BURST WRITE 3* BR
MASKED WRITE 3*
BW D, CW, MW
BW D, CW, MW
BR
* Command code inputs not shown from this state are not valid.
Figure 1. Functional State Diagram
MCM63P636 6
MOTOROLA FAST SRAM
D, CW, CR - MW
BR
HIGH-Z4
BW
INTERMEDIATE HIGH-Z1, 4 CR
DATA-IN (1)/ HIGH-Z1, 4 CW
MW
MASK (2)/ HIGH-Z1, 4 MW MW
INTERMEDIATE HIGH-Z1, 4 CR
DATA-IN (2)/ HIGH-Z1, 4 CW
MASK (3)/ HIGH-Z1, 4 MW MW
DATA-OUT/ Q(1)VALID1, 2 CR
DATA-IN (3)/ HIGH-Z1, 4 CW
MASK (4)/ HIGH-Z1, 4 MW
DATA-OUT/ Q(2)VALID1, 3 CR
DATA-IN (4)/ HIGH-Z1, 4 CW, MW
HIGH-Z1, 4 MW
DATA-OUT/ Q(3)VALID1, 2 BR
CR HIGH-Z1, 4 CW, MW
CR
DATA-OUT/ Q(4)VALID1, 3
DATA-OUT/ Q(4)VALID1, 3 D, CW, CR
BR
NOTES: 1. Command code inputs not shown from this state are not valid. 2. STRBA and STRBB transition from logic 1 to 0. STRBA and STRBB transition from logic 0 to 1. 3. STRBA and STRBB transition from logic 0 to 1. STRBA and STRBB transition from logic 1 to 0. 4. Data strobes are driven to High-Z.
Figure 2. Data I/O State Diagram
MOTOROLA FAST SRAM
MCM63P636 7
ABSOLUTE MAXIMUM RATINGS (See Note 1)
Rating Power Supply Voltage I/O Supply Voltage Input Supply Voltage Voltage Relative to VSS for Any Pin Except VDD Input Voltage (Three-State I/O) Output Current (per I/O) Package Power Dissipation Temperature Under Bias Storage Temperature Symbol VDD VDDQ VDDI Vin VIT Iout PD Tbias Tstg Value VSS - 0.5 to + 4.0 VSS - 0.5 to 2.5 VSS - 0.5 to 2.5 VSS - 0.5 to VDDI + 0.5 VSS - 0.5 to VDDQ + 0.5 20 2.75 - 10 to 85 - 55 to 125 Unit V V V V V mA W C C 5 2, 3 2, 3 2, 4 2, 4 Notes This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
NOTES: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. This is a steady-state DC parameter that is in effect after the power supply has achieved its nominal operating level. Power sequencing is not necessary. 3. VDDI = VDDQ. 4. Max Vin and VIT are not to exceed Max VDD. 5. Power dissipation capability is dependent upon package characteristics and use environment. See Package Thermal Characteristics.
PACKAGE THERMAL CHARACTERISTICS -- PBGA
Rating Junction to Ambient (@ 200 lfm) Junction to Board (Bottom) Junction to Case (Top) Symbol RJA RJB RJC Max 25 12 10 Unit C/W C/W C/W Notes 1, 2 3 4
PACKAGE THERMAL CHARACTERISTICS -- TQFP
Rating Junction to Ambient (@ 200 lfm) Junction to Board (Bottom) Junction to Case (Top) Symbol RJA RJB RJC Max 25 17 9 Unit C/W C/W C/W Notes 1, 2 3 4
NOTES: 1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, and board thermal resistance. 2. Per SEMI G38-87. 3. Indicates the average thermal resistance between the die and the printed circuit board. 4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC-883 Method 1012.1).
MCM63P636 8
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V 200 mV, TA = 0 to 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS AND DC CHARACTERISTICS (Voltage Referenced to VSS = 0 V)
Parameter Supply Voltage Input Supply Voltage I/O Supply Voltage Input Low Voltage (VDDI = VDDQ) Input High Voltage (VDDI = VDDQ) Input Leakage Current (0 V Vin VDD) Output Leakage Current (0 V Vin VDDQ) Output Low Voltage (IOL = 1 mA) Output High Voltage (IOL = - 1 mA) VIH Symbol VDD VDDI VDDQ VIL VIH Ilkg(I) Ilkg(O) VOL VOH Min 3.1 1.8 1.8 - 0.5 0.65 x VDDI -- -- - 0.5 VDDQ - 0.4 Typ 3.3 -- -- -- -- -- -- -- -- Max 3.5 2.2 2.2 0.35 x VDDI VDDI + 0.5 1 1 0.4 VDDQ + 0.5 Unit V V V V V A A V V
VSS VSS - 0.25 V VSS - 0.5 V 20% tKHKH
Figure 3. Undershoot Voltage SUPPLY CURRENTS
Parameter AC Supply Current (Device Selected, All Outputs Open, Freq = Max, VDD = Max) Input and I/O Supply Current - Desktop (All 40 Outputs Toggling, Freq = Max, VDDI = Max, VDDQ = Max, VDDI = VDDQ, Cdt = 24 pF) Static Standby Supply Current (Device Deselected, Freq = Max, VDD = Max, ADS (VDDI - 0.2 V), W Static (VSS + 0.2 V) or (VDDI - 0.2 V), SA and DQx Inputs Static (VSS + 0.2 V), Outputs Disabled) Idle Standby Supply Current (Device Deselected, Freq = 0, VDD = Max, ADS (VDDI - 0.2 V), W Static (VSS + 0.2 V) or (VDDI - 0.2 V), SA and DQx Inputs Static (VSS + 0.2 V), Outputs Disabled) Idle Input Standby Supply Current (Device Deselected, Freq = 0, VDD = Max, ADS (VDDI - 0.2 V), W Static (VSS + 0.2 V) or (VDDI - 0.2 V), SA and DQx Inputs Static (VSS + 0.2 V), Outputs Disabled) Symbol IDDA - 250 IDDA - 225 IDDA - 200 IDDQ - 250 IDDQ - 225 IDDQ - 200 ISB1 - 250 ISB1 - 225 ISB1 - 200 ISB2A Min -- Max TBD Unit mA Notes 1, 2, 3, 4 2, 5
--
311 280 249 63 57 50 TBD
mA
--
mA
1, 2, 4
--
mA
1, 3, 4
ISB2B
--
TBD
mA
1, 3, 5
NOTES: 1. Device is selected and deselected as defined by the Truth Table. 2. Reference AC Operating Conditions and Characteristics for input and timing. 3. Data states are all zero. 4. Includes supply current for VDD only. 5. Includes supply currents for VDDI and VDDQ only.
MOTOROLA FAST SRAM
MCM63P636 9
CAPACITANCE AND INDUCTANCE (See Notes 1, 2, and 3)
TQFP Capacitance (pF) Pin Description Pi D ii I/O Pins Data Strobe Pins Input Pins ADS Pin K and SK Pins TCK Boundary Scan Pin Boundary Scan Input Pins TDO Boundary Scan Pin Min 5 5 3 5 3.5 -- -- -- Max 7 7 5 7 4.5 -- -- -- Inductance (nH) Min 2 2 2 2 2 -- -- -- Max 10 10 10 10 10 -- -- -- PBGA Capacitance (pF) Min 5.5 5.5 3.5 5.5 4 -- -- -- Max 7.5 7.5 5.5 7.5 5 5 8 8 Inductance (nH) Min 2.5 2.5 2.5 2.5 1.5 -- -- -- Max 4.5 4.5 4 4.5 3 -- -- --
NOTES: 1. Parameters are periodically sampled rather than 100% tested. 2. Capacitance variation part to part on the same pin is 0.25 pF. 3. Inductance variation part to part on the same pin is 1 nH.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V 200 mV, Unless Otherwise Noted) AC TEST CONDITIONS
Parameter Input Timing Reference Level Input Pulse Levels Input Rise/Fall Time (20 to 80%) Output Timing Reference Level Die Temperature TJ-250 TJ-225 TJ-200 Value VDDQ/2 0 to 2.0 1 VDDQ/2 115 115 115 Unit V V V/ns V C
Z0 = 50 OUTPUT RL 1.0 V
Figure 4. AC Output Test Load
(TBD)
Figure 5. Lumped Capacitive Load and Typical Derating Curve
MCM63P636 10
MOTOROLA FAST SRAM
READ/WRITE CYCLE TIMING (See Notes 1 and 2)
MCM63P636-250 Parameter P Clock Cycle Time Clock High Time Clock Low Time Strobe Clock Cycle Time Strobe Clock High Time Strobe Clock Low Time Rising K to Rising SK Clock Access Time Clock to Output Low-Z Clock to Output High-Z Strobe Clock Access Time Setup Times: Address ADS Chip Enable Data In Data Out Write Address ADS Chip Enable Data In Data Out Write Symbol S bl tKHKH tKH tKL tSKHSKH tSKH tSKL tKHSKH tKHQV tKHQX tKHQZ tSKHSTV tAVKH tSVKH tEVKH tDVKH tQVSTV tWVKH tKHAX tKHSX tKHEX tKHDX tSTVQX tKHWX Min 4 1.06 1.06 4 1.06 1.06 1.6 -- 0 -- -- 0.5 1.2 0.5 1.2 1 1.2 4 0.5 4 0.5 1 0.5 Max -- -- -- -- -- -- 2.4 3.9 -- 3.9 3.9 -- MCM63P636-225 Min 4.4 1.24 1.24 4.4 1.24 1.24 1.8 -- 0 -- -- 0.5 1.5 0.5 1.5 1.1 1.5 4.4 0.5 4.4 0.5 1.1 0.5 Max -- -- -- -- -- -- 2.6 4.3 -- 4.3 4.3 -- MCM63P636-200 Min 5 1.46 1.46 5 1.46 1.46 2.1 -- 0 -- -- 0.5 1.5 0.5 1.5 1.15 1.5 5 0.5 5 0.5 1.15 0.5 Max -- -- -- -- -- -- 2.9 4.9 -- 4.9 4.9 -- ns ns ns ns ns Unit Ui ns ns ns ns ns ns Notes N 3, 4 4 4 3, 4 4 4 3 3 5, 6 5, 6 3 3
Hold Times:
--
--
--
ns
3
NOTES: 1. Reads and writes are as defined in the Truth Table. 2. All read and write cycle timings are referenced from K, SK, or data strobes. 3. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is given in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels. 4. Refer to Figure 5 for input reference levels. 5. This parameter is sampled and not 100% tested. 6. Measured at 200 mV from steady state.
VDDQ
tKH, tSKH
VIH VDDQ/2 VIL
tKL, tSKL
VSS
tKHKH, tSKHSKH
Figure 6. AC Timing Diagram Clock Reference
MOTOROLA FAST SRAM
MCM63P636 11
PULL-UP VOLTAGE (V) - 0.5 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 I (mA) MIN - 32 - 32 - 32 - 28 - 24 - 20 - 16 - 12 -8 -4 0 4 8 I (mA) MAX - 72 - 72 - 72 - 72 - 64 - 56 - 48 - 40 - 32 - 24 - 16 -8 0 0.2 0 0 - 32 CURRENT (mA) - 72 0.6 VOLTAGE (V) 1.8 1.6 2.2
(a) Pull-Up
PULL-UP VOLTAGE (V) - 0.5 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 I (mA) MIN - 10 0 4 8 12 16 20 24 28 28 28 28 28 I (mA) MAX - 20 0 8 16 24 32 40 48 56 64 72 72 72 0.2 0 0 28 CURRENT (mA) 72 0.6 VOLTAGE (V) 1.4 1.8 VDDQ
(b) Pull-Down Figure 7. Typical Output Buffer Characteristics - PBGA Only
MCM63P636 12
MOTOROLA FAST SRAM
PULL-UP VOLTAGE (V) - 0.5 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 I (mA) MIN - 23 - 23 - 23 - 20 - 17 - 14 - 11 -9 -6 -3 0 3 6 I (mA) MAX - 60 - 60 - 60 - 60 - 53 - 47 - 40 - 33 - 27 - 20 - 13 -7 0 0.2 0 0 - 23 CURRENT (mA) - 60 0.6 VOLTAGE (V) 1.8 1.6 2.2
(a) Pull-Up
PULL-UP VOLTAGE (V) - 0.5 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 I (mA) MIN -7 0 3 6 9 11 14 17 20 20 20 20 20 I (mA) MAX - 17 0 7 13 20 27 33 40 47 53 60 60 60 0.2 0 0 20 CURRENT (mA) 60 0.6 VOLTAGE (V) 1.4 1.8 VDDQ
(b) Pull-Down Figure 8. Typical Output Buffer Characteristics - TQFP Only
MOTOROLA FAST SRAM
MCM63P636 13
MCM63P636 14
READ CYCLES
t KHAX B t KHSX t KHWX t KHEX t KHQX Q(A) Q(A +1) Q(A + 2) Q(A + 3) t KHQZ t KHQV Q(B) Q(B + 1) Q(B + 2) Q(B + 3) t SKHSTV t QVSTV t STVQX
K
t AVKH
SA
A
t SVKH
ADS
t WVKH
W
t EVKH
E
DQx
SK
STRBA/B
STRBA/B
MOTOROLA FAST SRAM
NOTE: E low = SE1 and SE3 low and SE2 high.
WRITE CYCLES
MOTOROLA FAST SRAM
B t KHDX D(A) D(A + 1) D(A + 2) D(A + 3) D(B) D(B + 1)
K
SA
A
ADS
W
E
t DVKH
DQx
t KHSKH
SK
STRBA/B
STRBA/B
HIGH-Z
MCM63P636 15
MCM63P636 16
READ/WRITE CYCLES
B C Q(A) Q(A +1) Q(A + 2) Q(A + 3) D(B) D(B + 1) D(B + 2) D(B + 3) Q(C) Q(C + 1) Q(C + 2) Q(C + 3) BURST READ BURST WRITE BURST READ
K
SA
A
ADS
W
E
DQx
SK
STRBA/B
STRBA/B
MOTOROLA FAST SRAM
DESELECT
FUNCTIONAL OPERATION
POWER UP AND INITIALIZATION The RESET input is used to reset the SRAM internal logic at power on. At power on, this pin is held low and then driven high at some later time. Eight cycles after the RESET is asserted high, standard SRAM functionality may begin. DATA STROBES The data strobes STRBA, STRBA, STRBB, and STRBB are driven by the SRAM to be used by the device receiving the output data. The data strobes toggle only at the approximate center of each output data valid window such that the external device can reliably latch in this data. Following a burst read, the data strobes will be driven to High-Z. WRITE CYCLES The address is sampled on the first rising edge of clock of each burst write sequence, and the write data is sampled on the subsequent rising clock edges. During a burst write the last, last two, or last three addresses may be blocked from being written by asserting the W synchronous write pin high. However, once W is asserted high, it must remain in this state through the remainder of the burst write sequence. All burst write (and masked write) sequences must be followed by an inactive cycle to reset internal state machines. LOW POWER STOP-CLOCK OPERATION In the stop-clock mode of operation, the SRAM will hold all state and data values even though the clock is not running (full static operation). The SRAM design allows the clock to start with ADS, and stops the clock after the last write data is latched, or the last read data is driven out. When starting and stopping the clock, the initial clocks being driven may not meet the AC clock timing parametrics, but will meet those parametrics at least two clocks prior to ADS being asserted low. To achieve the lowest power operation for all three stop clock modes, stop read, stop write, and stop deselect: * Force the clock to a low state. * Force the control signals to an inactive state (this guarantees any potential source of noise on the clock input will not start an unplanned on activity). * Force the address inputs to a low state (VIL), preferably < 0.2 V.
STOP-CLOCK WITH READ TIMING
K VIL
ADS
VIH
SA HIGH-Z Din
A
VIL HIGH-Z VIL
B
Qout ADS INITIATES BURST READ
Q(A)
Q(A +1)
Q(A +2)
Q(A +3)
END BURST READ
K CLOCK STOP
STOP-CLOCK LOW POWER OPERATION
WAKE-UP/ INVALID INVALID CLOCK CLOCK
FIRST VALID CLOCK
MOTOROLA FAST SRAM
MCM63P636 17
STOP-CLOCK WITH WRITE TIMING
K VIL
ADS
VIH
SA
A
VIL
B
W
VIH
Din HIGH-Z
D(A)
D(A +1)
D(A +2)
D(A +3)
HIGH-Z VIL
Qout
ADS INITIATES BURST WRITE
END BURST WRITE
K CLOCK STOP
STOP-CLOCK LOW POWER OPERATION
WAKE-UP/ INVALID INVALID CLOCK CLOCK
FIRST VALID CLOCK
STOP-CLOCK WITH DESELECT TIMING
K VIL
ADS
VIH
SA
VIL
A
E HIGH-Z Din
VIL
Qout
Q(3)
Q(4)
CONTINUE END K BURST READ/ CLOCK READ DESELECT STOP
STOP-CLOCK LOW POWER OPERATION
WAKE-UP/ INVALID FIRST INVALID CLOCK VALID CLOCK CLOCK
MCM63P636 18
MOTOROLA FAST SRAM
SERIAL BOUNDARY SCAN TEST ACCESS PORT OPERATION
OVERVIEW The serial boundary scan test access port (TAP) on this RAM is designed to operate in a manner consistent with IEEE Standard 1149.1-1990 (commonly referred to as JTAG), but does not implement all of the functions required for IEEE 1149.1 compliance. Certain functions have been modified or eliminated because their implementation places extra delays in the RAMs critical speed path. Nevertheless, the RAM supports the standard TAP controller architecture (the TAP controller is the state machine that controls the TAPs operation) and can be expected to function in a manner that does not conflict with the operation of devices with IEEE Standard 1149.1 compliant TAPs. The TAP operates using a 2.5 V tolerant logic level signaling. DISABLING THE TEST ACCESS PORT It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfering with normal operation of the device, TRST should be tied low and TCK, TDI, and TMS should be pulled through a resistor to 2.0 V. TDO should be left unconnected.
TAP DC OPERATING CHARACTERISTICS
(TA = 0 to 70C, Unless Otherwise Noted)
Parameter Input Logic Low Input Logic High Input Leakage Current Output Logic Low Output Logic High NOTES: 1. 0 V Vin VDDQ for all logic input pins. 2. For VOL = 0.4 V, 14 mA IOL 28 mA. Symbol VIL1 VIH1 Ilkg VOL1 VOH1 Min - 0.5 0.65 x VDDQ -- VSS - 0.5 VDDQ - 0.4 Max 0.35 x VDDQ 2.5 10 0.4 VDDQ + 0.5 Unit V V A V V 1 2 Notes
MOTOROLA FAST SRAM
MCM63P636 19
TAP AC OPERATING CONDITIONS AND CHARACTERISTICS
(TA = 0 to 70C, Unless Otherwise Noted) AC TEST CONDITIONS
Parameter Input Timing Reference Level Input Pulse Levels Input Rise/Fall Time (20 to 80%) Output Timing Reference Level Output Load (See Figure 4 Unless Otherwise Noted) Value VDDQ/2 0 to 2.0 1 VDDQ/2 -- Unit V V V/ns V --
TAP CONTROLLER TIMING
Parameter TCK Cycle Time TCK Clock High Time TCK Clock Low Time TDO Access Time TRST Pulse Width Setup Times Capture TDI TMS Capture TDI TMS Symbol tTHTH tTH tTL tTLQV tTSRT tCS tDVTH tMVTH tCH tTHDX tTHMX Min 60 25 25 1 40 5 5 5 13 14 14 Max -- -- -- 10 -- -- Unit ns ns ns ns ns ns 1 Notes
Hold Times
--
ns
1
NOTE: 1. tCS and tCH define the minimum pauses in RAM I/O transitions to assure accurate pad data capture.
TAP CONTROLLER TIMING DIAGRAM
tTHTH tTLTH TEST CLOCK (TCK) tTHTL tMVTH TEST MODE SELECT (TMS) tTHDX tDVTH TEST DATA IN (TDI) tTLQV TEST DATA OUT (TDO) tTHMX
MCM63P636 20
MOTOROLA FAST SRAM
Boundary Scan Order
Bit No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 * Scans as logic 0. Signal Name DQa DQa DQa DQa DQa DQa DQa DQa DQa STRBA* STRBA* DQa DQa DQa DQa DQa DQa DQa DQa DQa SA SA SA SA SA1 SA0 SA SA SA SA SA SA NC* Bump ID 3D 1B 2B 1D 2D 1F 2F 1H 2H 3H 3K 2K 1K 2M 1M 2P 1P 2T 1T 3P 3T 4P 4R 4T 5R 5T 5M 5N 5P 6P 6R 6T 7T Bit No. 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 Signal Name DQb DQb DQb DQb DQb DQb DQb DQb DQb STRBB* STRBB DQb DQb DQb DQb DQb DQb DQb DQb DQb SA SA RESET ADS W K SE3 SK NU/VSS SE2 SE1 SA SA Bump ID 7P 8T 9T 9P 8P 9M 8M 9K 8K 7K 7H 8H 9H 8F 9F 8D 9D 8B 9B 7D 7A 7B 6C 5D 5C 5F 4B 5G 5J 5A 4A 3A 3B
MOTOROLA FAST SRAM
MCM63P636 21
TEST ACCESS PORT PINS
TCK -- TEST CLOCK (INPUT) Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS -- TEST MODE SELECT (INPUT) The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will not produce the same result as a logic one input level (not IEEE 1149.1 compliant). TDI -- TEST DATA IN (INPUT) The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction register (refer to Figure 10, TAP Controller State Diagram). An undriven TDI pin will not produce the same result as a logic one input level (not IEEE 1149.1 compliant). TDO -- TEST DATA OUT (OUTPUT) Output that is active depending on the state of the TAP state machine (refer to Figure 10, TAP Controller State Diagram). Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. TRST -- TAP RESET The TRST is an asynchronous input that resets the TAP controller and pre-loads the instruction register with the IDCODE command. This type of reset does not affect the operation of the system logic. The reset affects test logic only.
passed through the RAMs TAP to another device in the scan chain with as little delay as possible. BOUNDARY SCAN REGISTER The boundary scan register is identical in length to the number of active input and I/O connections on the RAM (not counting the TAP pins). This also includes a number of place holder locations (always set to a logic 0) reserved for density upgrade address pins. There are a total of 66 bits in the case of the x36 device. The boundary scan register, under the control of the TAP controller, is loaded with the contents of the RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to shift-DR state. The Bump/Bit Scan Order table describes which device bump connects to each boundary scan register location. The first column defines the bit's position in the boundary scan register. The shift register bit nearest TDO (i.e., first to be shifted out) is defined as bit 1. The second column is the name of the input or I/O at the bump and the third column is the bump number. IDENTIFICATION (ID) REGISTER The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in capture-DR state with the IDCODE command loaded in the instruction register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. ID Register Presence Indicator
Bit # Value 0 1
TEST ACCESS PORT REGISTERS
OVERVIEW The various TAP registers are selected (one at a time) via the sequences of ones and zeros input to the TMS pin as the TCK is strobed. Each of the TAPs registers are serial shift registers that capture serial input data on the rising edge of TCK and push serial data out on subsequent falling edge of TCK. When a register is selected it is "placed" between the TDI and TDO pins. INSTRUCTION REGISTER The instruction register holds the instructions that are executed by the TAP controller when it is moved into the run test/idle or the various data register states. The instructions are three bits long. The register can be loaded when it is placed between the TDI and TDO pins. The parallel outputs of the instruction register are automatically preloaded with the IDCODE instruction when TRST is asserted or whenever the controller is placed in the test-logic-reset state. The two least significant bits of the serial instruction register are loaded with a binary "or" pattern in the capture-IR state. BYPASS REGISTER The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be
Motorola JEDEC ID Code (Compressed Format, per IEEE Standard 1149.1-1990
Bit # Value 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 1 3 1 2 1 1 0
Reserved For Future Use
Bit # Value 16 0 15 0 14 0 13 1 12 0
Device Width
Bit # Value 20 0 19 0 18 1 17 1
Device Depth
Bit # Value 24 0 23 0 22 1 21 0
Revision Number
Bit # Value 31 0 30 0 29 0 28 0 27 0 26 0 25 1
Figure 9. ID Register Bit Meanings
MCM63P636 22
MOTOROLA FAST SRAM
TAP CONTROLLER INSTRUCTION SET
OVERVIEW There are two classes of instructions defined in the IEEE Standard 1149.1-1990; the standard (public) instructions and device specific (private) instructions. Some public instructions, are mandatory for IEEE 1149.1 compliance. Optional public instructions must be implemented in prescribed ways. Although the TAP controller in this device follows the IEEE 1149.1 conventions, it is not IEEE 1149.1 compliant because some of the mandatory instructions are not fully implemented. The TAP on this device may be used to monitor all input and I/O pads, but can not be used to load address, data, or control signals into the RAM or to preload the I/O buffers. In other words, the device will not perform IEEE 1149.1 EXTEST, INTEST, or the preload portion of the SAMPLE/PRELOAD command. When the TAP controller is placed in capture-IR state, the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the shift-IR state the instruction register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to update-IR state. The TAP instruction sets for this device are listed in the following tables.
possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results can not be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup, plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving the controller to shift-DR state then places the boundary scan register between the TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the update-DR state with the SAMPLE/PRELOAD instruction loaded in the instruction register has the same effect as the pause-DR command. This functionality is not IEEE 1149.1 compliant. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register, whatever length it may be in the device, is loaded with all logic 0s. EXTEST is not implemented in this device. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The IDCODE instruction is the default instruction loaded in at TRST assertion and any time the controller is placed in the test-logic-reset state.
STANDARD (PUBLIC) INSTRUCTIONS
BYPASS The BYPASS instruction is loaded in the instruction register when the bypass register is placed between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE/PRELOAD SAMPLE/PRELOAD is an IEEE 1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is loaded in the Instruction register, moving the TAP controller out of the capture-DR state loads the data in the RAMs input and I/O buffers into the boundary scan register. Because the RAM clock(s) are independent from the TAP clock (TCK), it is
THE DEVICE SPECIFIC (PUBLIC) INSTRUCTION
SAMPLE-Z If the HIGH-Z instruction is loaded in the instruction register, all DQ pins are forced to an inactive drive state (High-Z) and the bypass register is connected between TDI and TDO when the TAP controller. is moved to the shift-DR state.
THE DEVICE SPECIFIC (PRIVATE) INSTRUCTION
NO OP Do not use these instructions; they are reserved for future use.
MOTOROLA FAST SRAM
MCM63P636 23
STANDARD AND DEVICE SPECIFIC (PUBLIC) INSTRUCTION CODES
Instruction IDCODE HIGH-Z BYPASS SAMPLE/PRELOAD Code* 001** 010 011 100 Description Preloads ID register and places it between TDI and TDO. Does not affect RAM operation. Captures I/O ring contents. Places the bypass register between TDI and TDO. Forces all DQ pins to High-Z. NOT IEEE 1149.1 COMPLIANT. Places bypass register between TDI and TDO. Does not affect RAM operation. NOT IEEE 1149.1 COMPLIANT. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect RAM operation. Does not implement IEEE 1149.1 Preload function. NOT IEEE 1149.1 COMPLIANT.
* Instruction codes expressed in binary, MSB on left, LSB on right. ** Default instruction automatically loaded when TRST asserted or in test-logic-reset state.
STANDARD (PRIVATE) INSTRUCTION CODES
Instruction NO OP NO OP NO OP NO OP Code* 000 101 110 111 Description Do not use these instructions; they are reserved for future use. Do not use these instructions; they are reserved for future use. Do not use these instructions; they are reserved for future use. Do not use these instructions; they are reserved for future use.
* Instruction codes expressed in binary, MSB on left, LSB on right.
1
TEST-LOGIC RESET 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 0 1 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 1 0 0 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 0 0 1 1 1 1 SELECT IR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 0 1
0
NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK.
Figure 10. TAP Controller State Diagram
MCM63P636 24
MOTOROLA FAST SRAM
ORDERING INFORMATION
(Order by Full Part Number) MCM
Motorola Memory Prefix Part Number
63P636
XX
XXX
X
Blank = Trays, R = Tape and Reel Speed (250 = 250 MHz, 225 = 225 MHz, 200 = 200 MHz) Package (TQ = TQFP, ZP = PBGA)
Full Part Numbers -- MCM63P636TQ200 MCM63P636ZP200 MCM63P636ZP225 MCM63P636ZP250
MCM63P636TQ200R MCM63P636ZP200R MCM63P636ZP225R MCM63P636ZP250R
PACKAGE DIMENSIONS
ZP PACKAGE 9 x 17 BUMP PBGA CASE 1107-01
4X
0.20 (0.008) 0.15 (0.006) T 0.25 (0.010) T 0.035 (0.014) T
-T-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. MILLIMETERS MIN MAX 14.00 BSC 22.00 BSC --- 2.40 0.60 0.90 0.50 0.70 1.30 1.70 1.27 BSC 0.80 1.00 11.90 12.10 19.40 19.60 10.16 BSC 20.32 BSC INCHES MIN MAX 0.551 BSC 0.866 BSC --- 0.094 0.024 0.035 0.020 0.028 0.051 0.067 0.050 BSC 0.031 0.039 0.469 0.476 0.764 0.772 0.400 BSC 0.800 BSC
A -W-
P
B -L-
N TOP VIEW R
8X
U T R P N M L K J H G F E D C B A 123456789
DIM A B C D E F G K N P R S
G K
16X
G S
F E C SIDE VIEW
153X
D 0.30 (0.012) 0.10 (0.004)
S S
BOTTOM VIEW
TW T
S
L
S
MOTOROLA FAST SRAM
MCM63P636 25
TQ PACKAGE TQFP CASE 983A-01
4X
0.20 (0.008) H A-B D
2X 30 TIPS
e 0.20 (0.008) C A-B D e/2
-D-
80 81 51 50
B E/2 B VIEW Y E1 E E1/2
BASE METAL PLATING
-A-
-B-
-X- X=A, B, OR D
b1 c
100 1 30
31
D1/2 D1 D
2X 20 TIPS
D/2
0.13 (0.005)
0.20 (0.008) C A-B D
A -H- -C-
SEATING PLANE
q
2
0.10 (0.004) C
q
3 VIEW AB
0.05 (0.002)
S
S
q
1 0.25 (0.010)
GAGE PLANE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS D1 AND B1 DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE b DIMENSION TO EXCEED 0.45 (0.018). MILLIMETERS MIN MAX --- 1.60 0.05 0.15 1.35 1.45 0.22 0.38 0.22 0.33 0.09 0.20 0.09 0.16 22.00 BSC 20.00 BSC 16.00 BSC 14.00 BSC 0.65 BSC 0.45 0.75 1.00 REF 0.50 REF 0.20 --- 0.08 --- 0.08 0.20 0_ 7_ 0_ --- 11 _ 13 _ 11 _ 13 _ INCHES MIN MAX --- 0.063 0.002 0.006 0.053 0.057 0.009 0.015 0.009 0.013 0.004 0.008 0.004 0.006 0.866 BSC 0.787 BSC 0.630 BSC 0.551 BSC 0.026 BSC 0.018 0.030 0.039 REF 0.020 REF 0.008 --- 0.003 --- 0.003 0.008 0_ 7_ 0_ --- 11 _ 13 _ 11 _ 13 _
A2
R2
A1
R1
L2 L L1 VIEW AB
q
DIM A A1 A2 b b1 c c1 D D1 E E1 e L L1 L2 S R1 R2
q
1 2 q3
q q
MCM63P636 26
CCCC EEEE CCCC EEEE CCCC
b
M
c1
C A-B
S
D
S
SECTION B-B
MOTOROLA FAST SRAM
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shagawa-ku, Tokyo, Japan. 03-5487-8488
MfaxTM : RMFAX0@email.sps.mot.com - TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, Motorola Fax Back System - US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 - http://sps.motorola.com /mfax / HOME PAGE : http://motorola.com/sps / CUSTOMER FOCUS CENTER: 1-800-521-6274
MOTOROLA FAST SRAM
MCM63P636/D MCM63P636 27

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